Dual high-K oxides with SiGe channel

ABSTRACT

A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices ( 50, 52 ) and core transistor devices ( 51, 53 ) on a single substrate ( 15 ) having a silicon germanium channel layer ( 21 ) in the PMOS device areas ( 112, 113 ), where each DGO transistor device ( 50, 52 ) includes a metal gate ( 25 ), an upper gate oxide region ( 60, 84 ) formed from a second, relatively higher high-k metal oxide layer ( 24 ), and a lower gate oxide region ( 58, 84 ) formed from a first relatively lower high-k layer ( 22 ), and where each core transistor device ( 51, 53 ) includes a metal gate ( 25 ) and a core gate dielectric layer ( 72, 98 ) formed from only the second, relatively higher high-k metal oxide layer ( 24 ).

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed in general to the field ofsemiconductor devices. In one aspect, the present invention relates tothe fabrication of metal gate electrodes used in semiconductor devices.

2. Description of the Related Art

As semiconductor devices are scaled, aspects of device design andfabrication that previously gave rise to only second-order effects inlong-channel devices can no longer be ignored. For example, the scalingof channel length and gate oxide thickness in a conventional MOStransistor exacerbates problems of polysilicon gate depletion, high gateresistance, high gate tunneling leakage current and dopant (i.e., boron)penetration into the channel region of the device. As a result, CMOStechnology is increasingly replacing silicon dioxide gate dielectricsand polysilicon gate conductors with high dielectric constant (high-k)dielectrics in combination with metal gate electrodes formed from a gatestack of polysilicon and one or more metal layers. With suchtechnologies, the metal gate layers not only obviate gate-depletion andboron-penetration effects, but also provide a significantly lower sheetresistance.

While high-k dielectrics in conjunction with metal gate electrodesadvantageously exhibit improved transistor performance, the use of newmetal layer technologies can create new technical challenges. Forexample, when the threshold voltage for metal gate PMOS devices isadjusted by including a silicon germanium layer in the PMOS channelregion, the existing dual gate oxide (DGO) fabrication processes may notbe compatible if they use thermal oxidation or high temperature thermaloxidation process to form the thick gate oxide over the silicongermanium layer. This is because the high temperature process causes thegermanium to diffuse into the regions of the substrate or the gate oxidethat should not contain any germanium, thereby degrading the profile ofthe silicon germanium channel. Thermal oxidation of a silicon germaniumchannel layer can also create high interface state density that canadversely affect core and DGO device performance by creating a seriousTime-Dependent Dielectric Breakdown (TDDB) issue.

Accordingly, a need exists for an improved metal gate electrode andmanufacture method for an improved dual gate oxide device integrationwhich incorporates one or more high-k gate dielectric materials toovercome the problems in the art, such as outlined above. Furtherlimitations and disadvantages of conventional processes and technologieswill become apparent to one of skill in the art after reviewing theremainder of the present application with reference to the drawings anddetailed description which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be understood, and its numerous objects,features and advantages obtained, when the following detaileddescription is considered in conjunction with the following drawings, inwhich:

FIG. 1 is a partial cross-sectional view of a semiconductor waferstructure including a semiconductor layer;

FIG. 2 illustrates processing subsequent to FIG. 1 where a masking layeris formed over NMOS areas of the semiconductor wafer structure and anepitaxial SiGe layer is selectively formed over PMOS areas of thesemiconductor wafer structure;

FIG. 3 illustrates processing subsequent to FIG. 2 after the maskinglayer is removed and a first high-k gate dielectric layer is disposedover the semiconductor wafer structure;

FIG. 4 illustrates processing subsequent to FIG. 3 after a patternedetch mask is formed on the first high-k gate dielectric layer in the DGOdevice areas;

FIG. 5 illustrates processing subsequent to FIG. 4 after exposedportions of the first high-k gate dielectric layer are removed from thecore device areas;

FIG. 6 illustrates processing subsequent to FIG. 5 after the patternedetch mask is stripped or removed;

FIG. 7 illustrates processing subsequent to FIG. 6 after a second high-kgate dielectric layer is disposed over the semiconductor waferstructure;

FIG. 8 illustrates processing subsequent to FIG. 7 after a firstmetal-based gate layer is deposited over the semiconductor waferstructure;

FIG. 9 illustrates processing subsequent to FIG. 8 after asilicon-containing gate layer is disposed over the first metal-basedlayer; and

FIG. 10 illustrates processing subsequent to FIG. 9 after the singlemetal gate stack is selectively etched to form gate electrodes and theNMOS and PMOS core and DGO devices are at least partially completed.

DETAILED DESCRIPTION

A method and apparatus are described for integrating dual gate oxide(DGO) transistor devices and core transistor devices on a singlesubstrate where each transistor includes a metal gate and one or morehigh-k gate dielectric layers. As disclosed, a thicker gate dielectricis formed to include a first, relatively lower high-k layer and asecond, relatively higher high-k metal oxide layer in a region of thedevice for higher voltage requirements (e.g., an I/O region), and athinner second gate dielectric is formed with the second, relativelyhigher high-k metal oxide layer in a region of the device for lowervoltage requirements (e.g., a core device region). The substrate may beformed to include a channel layer in one or both of the PMOS and NMOSdevices areas, where the channel layer is formed from a semiconductormaterial having a different electrical property than the underlyingsemiconductor substrate (e.g., a SiC channel layer in the NMOS devicearea or a SiGe channel layer in the PMOS device area). When the PMOSdevices are formed on a SiGe channel layer, the threshold voltage ofPMOS metal-gate devices can be adjusted independently of NMOS devices.The DGO transistor devices may be fabricated to include a first,relatively lower high-k layer (e.g., Hafnium silicate or HfSiO_(x)N_(y))and a second, relatively higher high-k metal oxide layer (e.g., Hafniumoxide), while the core transistor devices may be fabricated using thesecond, relatively higher high-k metal oxide layer as the core gatedielectric layer. Finally, a single metal layer and polysilicon layerare sequentially formed or deposited over the DGO and core device areas,and then selectively etched to form PMOS and NMOS gate electrodes havingtuned the threshold voltages and improved gate oxide integrity.

Various illustrative embodiments of the present invention will now bedescribed in detail with reference to the accompanying figures. Whilevarious details are set forth in the following description, it will beappreciated that the present invention may be practiced without thesespecific details, and that numerous implementation-specific decisionsmay be made to the invention described herein to achieve the devicedesigner's specific goals, such as compliance with process technology ordesign-related constraints, which will vary from one implementation toanother. While such a development effort might be complex andtime-consuming, it would nevertheless be a routine undertaking for thoseof ordinary skill in the art having the benefit of this disclosure. Forexample, it is noted that, throughout this detailed description, certainlayers of materials will be deposited and removed to form the depictedsemiconductor structures. Where the specific procedures for depositingor removing such layers are not detailed below, conventional techniquesto one skilled in the art for depositing, removing or otherwise formingsuch layers at appropriate thicknesses shall be intended. Such detailsare well known and not considered necessary to teach one skilled in theart of how to make or use the present invention. In addition, selectedaspects are depicted with reference to simplified cross sectionaldrawings of a semiconductor device without including every devicefeature or geometry in order to avoid limiting or obscuring the presentinvention. Such descriptions and representations are used by thoseskilled in the art to describe and convey the substance of their work toothers skilled in the art. It is also noted that, throughout thisdetailed description, certain elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help improve theunderstanding of the embodiments of the present invention.

Referring now to FIG. 1, there is shown a partial cross-sectional viewof a semiconductor wafer structure 1. The structure 1 includes asemiconductor layer 16 formed on or as part of a semiconductor substrate15 that has a first crystallographic orientation. Also illustrated is aplurality of shallow trench isolations 17 that divide the layer 16 intoseparate regions, such as an NMOS dual gate oxide (N-DGO) region 110, anNMOS core (N-Core) region 111, a PMOS dual gate oxide (P-DGO) region112, and a PMOS core (P-Core) region 113. Although not shown, thematerials of layer 16 for NMOS device areas 110, 111 and PMOS deviceareas 112, 113 may be different. For example, the N-DGO region 110 andN-Core region 111 may be implanted with boron to form P-well regions,and the P-DGO region 112 and PMOS core region 113 may be implanted witharsenic or phosphorus to form N-well regions (not shown). NMOS devicesmay be formed in N-DGO region 110 and N-Core region 111. PMOS devicesmay be formed in P-DGO region 112 and P-Core region 113. The devicesformed in the dual gate oxide regions (110 and 112) will be formed withthicker gate oxide and the devices formed in the core regions (111 and113) will be formed with thinner gate oxide.

Depending on the type of transistor device being fabricated, thesemiconductor layer 15, 16 may be implemented as a bulk siliconsubstrate, single crystalline silicon (doped or undoped), semiconductoron insulator (SOI) substrate, or any semiconductor material including,for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, as well as otherIII/V or II/VI compound semiconductors or any combination thereof, andmay optionally be formed as the bulk handling wafer. The semiconductorlayer 15, 16 has a channel crystallographic orientation of <100>. Thepresent disclosure will also work for devices with other crystalorientation such as <110>, <111> which may be desirable for enhancingcarrier mobility. For any FET type (NMOS or PMOS), the layer 16 mayconsist of multiple stacks of materials. Of note is that although bulktype of substrate is shown here for the description of the invention,the invention is not limited to any specific substrate type. Forexample, the starting substrate for the invention can be ofsemiconductor-on-insulator (SOI) type having a buried insulator layerunder a top layer of semiconductor, or a dual substrate orientationsubstrate, such as partial bulk and partial SOI with orientationdifferent for bulk and SOI.

The isolation regions or structures 17 are formed to electricallyisolate the NMOS device areas 110, 111 from the PMOS device areas 112,113. Isolation structures 17 define lateral boundaries of an activeregion or transistor region 110-113 in active layer 16, and may beformed using any desired technique, such as selectively etching anopening in the second semiconductor layer 16 using a patterned mask orphotoresist layer (not shown), depositing a dielectric layer (e.g.,oxide) to fill the opening, and then polishing the deposited dielectriclayer until planarized with the remaining second semiconductor layer 16.Any remaining unetched portions of the patterned mask or photoresistlayer(s) are stripped. As will be appreciated, the isolation regions orstructures 17 may be formed in other ways in other embodiments.

FIG. 2 illustrates processing of a semiconductor wafer structure 2subsequent to FIG. 1 where a patterned masking layer 20 is selectivelyformed over NMOS areas 110, 111 of the semiconductor wafer structure andan epitaxial SiGe layer 21 is selectively formed over PMOS areas 112,113 of the semiconductor wafer structure. For example, one or moremasking layers 20 (e.g., an oxide layer and/or nitride layer) may bedeposited and/or grown over the semiconductor wafer structure, and thenconventional patterning and etching techniques may be used to form anopening in the mask layer(s) 20 that exposes at least the PMOS devicearea 112, 113. The selectively formed masking layer 20 is used to defineand differentiate active regions for NMOS and PMOS devices subsequentlyformed on the wafer structure 16. After forming the patterned maskinglayer 20, a thin, compressively stressed semiconductor layer 21 isselectively formed over the PMOS area(s) 112, 113 of the semiconductorwafer structure that will be used to form the PMOS devices. Though thesemiconductor layer 21 is shown in the figures as being formed on top ofthe semiconductor layer 16, it will be appreciated that thesemiconductor layer 21 may be embedded in the semiconductor layer 16. Inselected embodiments, the thin, compressively stressed semiconductorlayer 21 is formed with a semiconductor material having largeratom-to-atom spacing than the underlying second semiconductor layer 16,such as SiGe, SiGeC, or combinations and composition by weight thereof,which is capable of being formed utilizing a selective epitaxial growthmethod or other deposition methods accompanied by subsequentre-crystallization. For example, if PMOS devices are formed over thesemiconductor layer 16 in the PMOS area 112, 113 and the semiconductormaterial for layer 16 is silicon, the semiconductor layer 21 may beformed by epitaxially growing a SiGe layer that is thinner than acritical relaxation thickness to form a compressive SiGe layer 21. Thisepitaxial growth may be achieved by a process of chemical vapordeposition (CVD) at a chamber temperature between 400 and 900° C. in thepresence of dichlorosilane, germane (GeH₄), HCl, and hydrogen gas. Solong as the thickness of the SiGe layer 21 is less than the criticalrelaxation thickness, the SiGe layer 21 is compressively stressed. Aswill be appreciated, the critical relaxation thickness for a SiGe layerwill depend on the amount of germanium contained in the layer 21 and thelayer thickness. In an example embodiment, an epitaxially grown SiGelayer 21 that has 10% to 50% germanium (e.g., 20% to 35% germanium) andthat is grown to a predetermined thickness in a range of at least 30Angstroms to 150 Angstroms (e.g., approximately 100 Angstroms) will havea biaxial compressive strain because of the lattice mismatch betweenlayers 22 and 16. Compressive stress and lower band gap of SiGe allowsfor threshold voltage lowering and mobility enhancement for PMOS devicesin regions 112 and 113. In addition, SiGe can be doped with Boron forfurther reduction of PMOS threshold voltage. Although a channel layer 21of silicon germanium may be formed, it will be appreciated that othersemiconductor materials having different electrical properties fromsemiconductor substrate 16 may be used. For example, in one embodiment,silicon carbide may be used, or any semiconductor material may be usedthat changes a band gap of a channel region for NMOS devices. In anotherembodiment, any semiconductor material that changes a band gap of achannel region of a thick gate device relative to a channel region of athin gate device may be used. Though not shown, it will be appreciatedthat a semiconductor cap layer may be formed over the epitaxialsemiconductor layer 21 by epitaxially growing or depositing a layer ofsilicon to a predetermined thickness of approximately 15 Angstroms overthe underlying SiGe layer 22, though other thicknesses and materials maybe used.

FIG. 3 illustrates processing of a semiconductor wafer structure 3subsequent to FIG. 2 after the mask layer 20 is removed, and a firsthigh-k gate dielectric layer 22 is disposed over the semiconductor waferstructure. In selected embodiments, the first high-k gate dielectriclayer 22 is formed by depositing a high-k gate dielectric material witha relatively low dielectric constant value on top of the DGO deviceareas and the core device areas 110-113 using chemical vapor deposition(CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapordeposition (PVD), atomic layer deposition (ALD), or any combination(s)of the above. In selected embodiments, the first high-k gate dielectriclayer 22 may be formed by a low temperature CVD or ALD process to apredetermined final thickness in the range of 1-100 Angstroms (e.g.,10-50 Angstroms, or more particularly, 20-30 Angstroms), though otherthicknesses may be used. A suitable high-k gate dielectric material forthe gate dielectric layer 22 is an insulator material having adielectric constant value k of 7.0 or greater that is lower than thedielectric constant value of the second high-k gate dielectric layer 24(described below). A suitable temperature for the deposition process isin the range of approximately 200 degrees Celsius to approximately 400degrees Celsius, and is controlled to reduce or eliminate the diffusionof germanium. A suitable high-k gate dielectric material for use as thefirst high-k gate dielectric layer 22 is a hafnium-based dielectricwhich does not adversely interact with the underlying silicon germaniumlayer 21, such as hafnium silicate (e.g., Hf_(x)Si_(1-x)O_(y)) orhafnium oxy-nitride (e.g., Hf_(x)Si_(1-x)O_(y)N_(z)), though othersilicates of zirconium, aluminum, lanthanum, strontium, tantalum,titanium and combinations thereof may also be used, including but notlimited to HfSiO_(x), ZrSiO_(x), LaSiO_(x), YSiO_(x), ScSiO_(x),CeSiO_(x), and HfLaSiO_(x). In addition, multi-metallic oxides (forexample barium strontium titanate, BST) may also provide high-kdielectric properties. As will be appreciated, the first high-k gatedielectric layer 22 may be formed in other ways in other embodiments.

FIG. 4 illustrates processing of a semiconductor wafer structure 4subsequent to FIG. 3 after a patterned etch mask 23 is formed on thefirst high-k gate dielectric layer 22 in the DGO device areas 110, 112.The patterned etch mask 23 may be formed by applying a layer ofphotoresist that is patterned directly on the first high-k gatedielectric layer 22 to mask the DGO device areas 110, 112, or amulti-layer masking technique may be used to form a etch mask pattern 23over the first high-k gate dielectric layer 22 in the DGO device areas110, 112.

FIG. 5 illustrates processing of a semiconductor wafer structure 5subsequent to FIG. 4 after exposed portions of the first high-k gatedielectric layer 22 are removed from the core device areas 111, 113. Inparticular, with the patterned resist or mask layer 23 in place, theexposed portions of the first high-k gate dielectric layer 22 areselectively etched and removed from the core device areas 111, 113,thereby leaving portions of the first high-k gate dielectric layer 22 inthe DGO device areas 110, 112. The pattern transfer and etching of themask layer 23 may use one or more etching steps to remove theunprotected portions of the layer 22, including a dry etching processsuch as reactive-ion etching, ion beam etching, plasma etching or laseretching, a wet etching process wherein a chemical etchant is employed orany combination thereof. For example, the exposed portion of firsthigh-k gate dielectric layer 22 may be anisotropically etched using areactive ion etch process, leaving the lower gate oxide region 22 inN-DGO region 110 and in the P-DGO region 112. In other embodiments, theexposed portions of the first high-k gate dielectric layer 22 may beremoved from N-Core region 111 and P-Core region 113 using ahydrofluoric acid (HF) clean, such as a diluted HF clean process.

After the mask etch process, the patterned photoresist layer 23 isremoved. This is shown in FIG. 6 which illustrates processing of asemiconductor wafer structure 6 subsequent to FIG. 5 after the patternedetch mask 23 is stripped or removed, such as by using, for example, apiranha clean or solvent clean process.

FIG. 7 illustrates processing of a semiconductor wafer structure 7subsequent to FIG. 6 after a second high-k gate dielectric layer 24 isdisposed over the semiconductor wafer structure. Prior to forming thesecond high-k gate dielectric layer 24, a pre-cleaning process (e.g., anRCA standard clean 1 or 2 solution without HF) may be applied to clearthe top surfaces of the relevant regions. As illustrated, the secondhigh-k gate dielectric layer 24 is formed by depositing a high-k gatedielectric material with a relatively high dielectric constant value ontop of the DGO device areas and the core device areas 110-113 so thatthe dielectric layer 24 directly overlies the lower gate oxide region 22in the N-DGO region 110, a portion of the semiconductor layer 16 inN-Core region 111, the lower gate oxide region 22 in the P-DGO region112, and the SiGe layer 21 in the P-Core region 113. In selectedembodiments, the second high-k gate dielectric layer 24 is depositedusing CVD, PECVD, PVD, ALD, or any combination(s) of the above to apredetermined final thickness in the range of 1-100 Angstroms (e.g.,10-50 Angstroms, or more particularly, 15-20 Angstroms), though otherthicknesses may be used. A suitable high-k gate dielectric material forthe gate dielectric layer 24 is an insulator material having adielectric constant value k greater than 7.0 that is higher than thedielectric constant value of the first high-k gate dielectric layer 22.For example, a metal oxide compound may be used that does not includesilicon (e.g., HfO₂), though other oxides, silicates or aluminates ofzirconium, aluminum, lanthanum, strontium, tantalum, titanium andcombinations thereof may also be used, including but not limited toTa₂O₅, ZrO₂, TiO₂, Al₂O₃, Y₂O₃, La₂O₃, HfSiN_(y)O_(x), ZrSiN_(y)O_(x),ZrHfO_(x), LaSiO_(x), YSiO_(x), ScSiO_(x), CeSiO_(x), HfLaSiO_(x),HfAlO_(x), ZrAlO_(x), and LaAlO_(x). In addition, multi-metallic oxides(for example barium strontium titanate, BST) may also provide high-kdielectric properties. As will be appreciated, the second high-k gatedielectric layer 24 may be formed in other ways in other embodiments.

Next, as shown in FIG. 8 which illustrates processing of a semiconductorwafer structure 8 subsequent to FIG. 7, a first metal-based gate layer25 is deposited on the second high-k gate dielectric layer 24. Inselected embodiments, the metal-based layer 25 is deposited on thesecond high-k gate dielectric layer 24 using any desired deposition orsputtering process, such as CVD, PECVD, PVD, ALD, molecular beamdeposition (MBD) or any combination(s) thereof A suitable material foruse as the metal-based layer 25 is an element or alloy (e.g., TaC or W)which may be deposited over the NMOS and PMOS regions 110-113 to apredetermined thickness of 20-150 Angstroms (e.g., 50-100 Angstroms),though other metallic layer materials with different thicknesses may beused. In selected embodiments, the metal-based layer 25 may include anelement selected from the group consisting of Ti, Ta, La, Ir, Mo, Ru, W,Os, Nb, Ti, V, Ni, W, and Re to form a metal or metal-based layer thatmay contain carbon and/or nitrogen (such as TiN, TaC, HfC, TaSi, ZrC,Hf, etc.) or even a conductive metal oxide (such as IrO₂).

FIG. 9 illustrates processing of a semiconductor wafer structure 9subsequent to FIG. 8 after a silicon-containing gate layer 26 isdisposed over the metal-based layer 25 to form a metal gate stack. Inselected embodiments, the silicon-containing layer 26 is an amorphous orpolysilicon cap layer or an amorphous/poly silicon germanium cap layerthat is formed using CVD, PECVD, PVD, ALD, MBD, or any combination(s)thereof to a predetermined thickness in the range of 200-1000 Angstroms(e.g., 500-600 Angstroms), though other materials and thicknesses may beused. Silicon-containing layer 26 may also be a doped or undopedamorphous silicon or silicon germanium layer. An anti-reflective coating(ARC) (not shown) may subsequently be formed over silicon-containinggate layer 26 to a thickness in the range of approximately 10 to 200Angstroms, though other thicknesses may be used. In a selectedembodiment, ARC layer is formed by depositing a silicon-rich siliconnitride layer, an organic ARC, a silicon-oxy nitride, or any ARCmaterial which serves an ARC function for the particular lithographyprocess. As will be appreciated, ARC layer may be applied directly tothe silicon-containing layer 26 or as part of a multilayer mask on thesilicon-containing layer 26. As deposited, the amorphoussilicon-containing layer 26 covers the NMOS and PMOS device area110-113.

FIG. 10 illustrates processing of a semiconductor wafer structure 10subsequent to FIG. 9 after PMOS and NMOS devices 50-53 are formed. As apreliminary step, the metal gate stack is selectively etched to formNMOS and PMOS gate electrodes in the core and DGO device regions 110-113using any desired pattern and etching processes, including applicationand patterning of photoresist directly on the ARC layer, thoughmulti-layer masking techniques may also be used. By way of example,N-DGO device 50 may be formed in N-DGO region 110, N-Core device 51 maybe formed in N-Core region 111, P-DGO device 52 may be formed in P-DGOregion 112, and P-Core device 53 may be formed in P-Core region 113.These devices may be formed by forming gate electrodes, spacers, andsource/drain regions using conventional semiconductor processing steps.Thus, for example, N-DGO device 50 may include a gate structureincluding a lower gate oxide region 58 (formed from the first relativelylower high-k layer 22), an upper gate oxide region 60 (formed from thesecond relatively higher high-k layer 24), a metal gate electrode region62, and a polysilicon gate electrode region 64. N-DGO device 50 mayfurther include spacers 66 formed adjacent to the gate structure. N-DGOdevice 50 may further include source/drain regions 68 and 70 that areimplanted at least in part around the gate structure and/or spacers 66.N-Core device 51 may include a gate structure including a gate oxideregion 72 (formed from the second relatively higher high-k layer 24), ametal gate electrode region 74, and a polysilicon gate electrode region76. N-Core device 52 may further include spacers 78 formed adjacent tothe gate structure, and source/drain regions 80 and 82 that areimplanted at least in part around the gate structure and/or spacers 78.P-DGO device 52 may include silicon germanium region 30. P-DGO device 52may further include a gate structure including a lower gate oxide region84 (formed from the first relatively lower high-k layer 22), an uppergate oxide region 86 (formed from the second relatively higher high-klayer 24), a metal gate electrode region 88, and a polysilicon gateelectrode region 90. P-DGO device 52 may further include spacers 92formed adjacent to the gate structure and source/drain regions 94 and 96that are implanted at least in part around the gate structure and/orspacers 92. P-Core device 53 may include silicon germanium region 32.P-Core device 53 may further include a gate structure including a gateoxide region 98 (formed from the second relatively higher high-k layer24), a metal gate electrode region 100, and a polysilicon gate electroderegion 102. P-Core device 53 may further include spacers 104 formedadjacent to the gate structure and source/drain regions 106 and 108 thatare implanted at least in part around the gate structure and/or spacers104.

As described herein, the inclusion of the lower gate oxide regions 58,84 in the DGO NMOS and PMOS devices 50, 52 improves the interfacequality with the upper gate oxide regions 60, 84 because of the materialsimilarity between the first high-k gate dielectric layer 22 (e.g.,HfSiO_(x)) and the second high-k gate dielectric layer 24 (e.g., HfO₂).In addition, by forming the lower gate oxide regions 58, 84 from a firsthigh-k gate dielectric layer 22 having a relatively lower k (e.g.,HfSiO_(x)), the physical thickness increase required to meet desiredelectrical oxide thickness (Tox) is minimized, thus ensuring better filmquality. Finally, the formation of the lower gate oxide regions 58, 84with a relatively low temperature deposition of the first high-k gatedielectric layer 22 reduces the germanium diffusion from the silicongermanium channel layer which leads to high interface state density andTDDB problems, as compared to forming a gate dielectric layer with ahigh temperature thermal oxide process. In addition, the formation ofthe gate oxide regions 72, 98 with the second relatively higher high-klayer 24 provides improved core device performance for the N-Coredevices 51 and P-Core devices 53.

As will be appreciated, additional or different processing steps may beused to complete the fabrication of the depicted device structures 50-53into functioning devices. In addition to various front end processingsteps (such as sacrificial oxide formation, stripping, isolation regionformation, gate electrode formation, extension implant, halo implant,spacer formation, source/drain implant, annealing, silicide formation,and polishing steps), additional backend processing steps may beperformed, such as forming contact plugs and multiple levels ofinterconnect(s) that are used to connect the device components in adesired manner to achieve the desired functionality. Once the waferfabrication process is completed, the wafer can be singulated or dicedinto separate integrated circuits dies for subsequent electricalconnection, such as by leadframe attachment, wirebonding andencapsulation. Thus, the specific sequence of steps used to complete thefabrication of the device components may vary, depending on the processand/or design requirements.

By now, it should be appreciated that there has been provided herein asemiconductor fabrication process for integrating DGO and coretransistors on a single substrate. In the disclosed methodology, a waferis provided that includes a first semiconductor layer as asemiconductor-on-insulator (SOI) substrate structure or bulk substratestructure with PMOS and NMOS device areas which include a DGO NMOSdevice area, an NMOS core device area, a DGO PMOS device area and a PMOScore device area. On at least part of the first semiconductor layer, acompressive silicon germanium layer is formed, such as by epitaxiallygrowing silicon germanium to a predetermined thickness. On thecompressive silicon germanium layer for P-DGO and Silicon for N-DGO, adeposited first high-k dielectric layer is selectively formed from afirst dielectric material (e.g., a silicate or metal oxynitridematerial, such as Hf_(x)Si_(1-x)O_(y) or Hf_(x)Si_(1-x)O_(y)N_(z)) whichhas a first dielectric constant value greater than 7.0. The selectiveformation of the first high-k dielectric layer may include blanketdepositing the first high-k dielectric layer over the NMOS device areaand the PMOS device area (including the compressive silicon germaniumlayer in the PMOS device area), followed by forming a patterned etchmask to cover the compressive silicon germanium layer and thenselectively etching the first high-k dielectric layer to expose the NMOSdevice area while leaving the first high-k dielectric layer over thecompressive silicon germanium layer. In selected embodiments, a lowtemperature deposition process is used to deposit the silicate or metaloxy-nitride material where the temperature is selected to reduce oreliminate germanium diffusion from the compressive silicon germaniumlayer. Subsequently, a second high-k dielectric layer is deposited overthe PMOS and NMOS device areas, where the second high-k dielectric layeris formed from a second dielectric material which has a dielectricconstant value that is higher than the first dielectric constant value.For example, the second high-k dielectric layer may be a layer of HfO₂that is deposited over the first high-k dielectric layer in the PMOSdevice area and over the first semiconductor layer in the NMOS devicearea. The process further includes depositing one or more gate electrodelayers over the second high-k dielectric layer.

In another form, there is provided a method of forming devices. In thedisclosed methodology, a first gate dielectric device is formed in afirst (DGO) region of a semiconductor substrate, where a compressivesilicon germanium layer or silicon carbide layer may be epitaxiallygrown on a first channel region. In forming the first gate dielectricdevice, a first gate dielectric formed is formed by depositing a firsthigh-k dielectric layer (e.g., Hf_(x)Si_(1-x)O_(y) orHf_(x)Si_(1-x)O_(y)N_(z)) and a second high-k dielectric layer (e.g.,HfO₂) over the silicon germanium layer in the first channel region ofthe semiconductor substrate, where the first high-k dielectric layer hasa first dielectric constant value that is smaller than a seconddielectric constant value for the second high-k dielectric layer. Inselected embodiments, the first high-k dielectric layer is deposited asa silicate or metal oxy-nitride material in a deposition process whichoccurs at a temperature that is selected to reduce or eliminategermanium diffusion from the compressive silicon germanium layer. Inaddition, a gate electrode material is deposited over the second high-kdielectric layer. The disclosed methodology also forms a second gatedielectric device in a second (core) region of the semiconductorsubstrate by forming a second gate dielectric that is thinner than thefirst gate dielectric and that is formed by depositing the second high-kdielectric layer (e.g., HfO₂) over a second channel region of thesemiconductor substrate. In addition, a gate electrode material isdeposited over the second high-k dielectric layer. Finally, thedisclosed methodology may also form a third gate dielectric device in athird (DGO) region of the semiconductor substrate that includes a thirdgate dielectric formed by sequentially depositing the first and secondhigh-k dielectric layers over a third channel region of thesemiconductor substrate. In addition, a fourth gate dielectric devicemay be formed in a fourth (core) region of the semiconductor substratethat includes a fourth gate dielectric that is thinner than the thirdgate dielectric and that is formed by depositing the second high-kdielectric layer over a fourth channel region of the semiconductorsubstrate.

In yet another form, there is provided a method for forming asemiconductor device on a semiconductor substrate having first andsecond device areas (e.g., DGO and core device areas). As disclosed, acompressive silicon germanium layer may be epitaxially grown on one ormore PMOS channel regions of the semiconductor substrate (e.g., in thefirst and/or second device areas). Subsequently, a first high-kdielectric layer having a first dielectric constant value of 7.0 orgreater is formed over the first device area, such as by depositing alayer of Hf_(x)Si_(1-x)O_(y) or Hf_(x)Si_(1-x)O_(y)N_(z) on the silicongermanium layer with a deposition process which occurs at a temperaturethat is selected to reduce or eliminate germanium diffusion from thecompressive silicon germanium layer. To form the first high-k dielectriclayer in the first area, the first high-k dielectric layer may bedeposited as a layer of silicate or metal oxy-nitride over the first andsecond device areas, and then selectively etched from the second devicearea to expose the semiconductor substrate in the second device area. Inaddition, a second high-k dielectric layer (e.g., HfO₂) is formed overthe first high-k dielectric layer in the first device area and over thesemiconductor substrate in the second device area, where the secondhigh-k dielectric layer has a dielectric constant value that is higherthan the first dielectric constant value. One or more gate electrodelayers are then over the second high-k dielectric layer and selectivelyetched to form one or more gate electrode structures over the first andsecond device areas. By forming the first high-k dielectric layer overthe first device area with a relatively lower dielectric constant value,there is a reduction in the thickness measure for the first high-kdielectric layer in the first device area that is required to meet apredetermined electrical oxide thickness (Tox) requirement as comparedto forming the first high-k dielectric layer with a material having ahigher dielectric constant value.

Although the described exemplary embodiments disclosed herein aredirected to various semiconductor device structures and methods formaking same, the present invention is not necessarily limited to theexample embodiments which illustrate inventive aspects of the presentinvention that are applicable to a wide variety of semiconductorprocesses and/or devices. For example, although the process flow isdescribed above with respect to PMOS devices having silicon germaniumregions, a similar process flow may be used with NMOS devices havingsilicon carbon. In the NMOS device process flow, the semiconductor layer21 could be formed as a silicon carbide layer to change a band gap of anNMOS channel region, in which case the DGO device 52 would be formed asan N-DGO device, and the core device 53 would be formed as an N-Coredevice. Thus, the particular embodiments disclosed above areillustrative only and should not be taken as limitations upon thepresent invention, as the invention may be modified and practiced indifferent but equivalent manners apparent to those skilled in the arthaving the benefit of the teachings herein. For example, the methodologyof the present invention may be applied using materials other thanexpressly set forth herein. In addition, the invention is not limited toany particular type of integrated circuit described herein. Accordingly,the foregoing description is not intended to limit the invention to theparticular form set forth, but on the contrary, is intended to coversuch alternatives, modifications and equivalents as may be includedwithin the spirit and scope of the invention as defined by the appendedclaims so that those skilled in the art should understand that they canmake various changes, substitutions and alterations without departingfrom the spirit and scope of the invention in its broadest form.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any element(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature or element of any or all the claims. As used herein, the terms“comprises,” “comprising,” or any other variation thereof, are intendedto cover a non-exclusive inclusion, such that a process, method,article, or apparatus that comprises a list of elements does not includeonly those elements but may include other elements not expressly listedor inherent to such process, method, article, or apparatus.

What is claimed is:
 1. A semiconductor fabrication process comprising:providing a wafer comprising a first semiconductor layer having a firstPMOS device area, a second PMOS device area, and an NMOS device area;forming a compressive silicon germanium layer on at least the first PMOSdevice area, and the second PMOS device area; selectively forming adeposited first high-k dielectric layer over the compressive silicongermanium layer of the first PMOS device area, where the first high-kdielectric layer is formed from a first dielectric material which has afirst dielectric constant value of 7.0 or greater; depositing a secondhigh-k dielectric layer over the first high-k dielectric layer in thefirst PMOS device area, over the compressive silicon germanium layer inthe second PMOS device area, and over the first semiconductor layer inthe NMOS device area, where the second high-k dielectric layer is formedfrom a second dielectric material which has a dielectric constant valuethat is higher than the first dielectric constant value; and depositingone or more gate electrode layers over the second high-k dielectriclayer wherein a first device formed in the first PMOS device area ischaracterized as a PMOS transistor that includes a portion of thedeposited first high-k dielectric layer and a portion of the secondhigh-k dielectric layer and a second device formed in the second PMOSdevice area is characterized as a PMOS transistor that includes aportion of the second high-k dielectric layer and does not include aportion of the deposited first high-k dielectric layer.
 2. Thesemiconductor fabrication process of claim 1, where providing the wafercomprises providing a first semiconductor layer as asemiconductor-on-insulator (SOI) substrate structure or bulk substratestructure.
 3. The semiconductor fabrication process of claim 1, whereforming the compressive silicon germanium layer comprises epitaxiallygrowing silicon germanium to a predetermined thickness.
 4. Thesemiconductor fabrication process of claim 1, where selectively formingthe deposited first high-k dielectric layer comprises depositing asilicate or metal oxy-nitride material.
 5. The semiconductor fabricationprocess of claim 1, where selectively forming the deposited first high-kdielectric layer comprises depositing a layer of Hf_(x)Si_(1-x)O_(y) orHf_(x)Si_(1-x)O_(y)N_(z) over at least the compressive silicon germaniumlayer.
 6. The semiconductor fabrication process of claim 1, whereselectively forming the deposited first high-k dielectric layercomprises depositing a silicate or metal oxy-nitride material in adeposition process which occurs at a temperature that is selected toreduce or eliminate germanium diffusion from the compressive silicongermanium layer.
 7. The semiconductor fabrication process of claim 1,where selectively forming the deposited first high-k dielectric layercomprises: blanket depositing the first high-k dielectric layer over thefirst PMOS device area, the second PMOS device area, and the NMOS devicearea; forming a patterned etch mask to cover the compressive silicongermanium layer in the first PMOS device area; and selectively etchingthe first high-k dielectric layer to expose the NMOS device area and thesecond PMOS device area while leaving the first high-k dielectric layerover the compressive silicon germanium layer in the first PMOS devicearea.
 8. The semiconductor fabrication process of claim 1, wheredepositing the second high-k dielectric layer comprises depositing alayer of HfO₂ over the first high-k dielectric layer in the first PMOSdevice area and over the first semiconductor layer in the NMOS devicearea, and over the compressive silicon germanium layer in the secondPMOS device layer.
 9. A method of forming devices comprising: forming afirst gate dielectric device in a first region of a semiconductorsubstrate, wherein the first gate dielectric device comprises a firstgate dielectric formed by depositing a first high-k dielectric layer anda second high-k dielectric layer over a first channel region of thesemiconductor substrate, where the first high-k dielectric layer has afirst dielectric constant value that is smaller than a second dielectricconstant value for the second high-k dielectric layer; and forming asecond gate dielectric device in a second region of the semiconductorsubstrate, wherein the second gate dielectric device comprises a secondgate dielectric that is thinner than the first gate dielectric and thatis formed by depositing the second high-k dielectric layer over a secondchannel region of the semiconductor substrate; wherein the first channelregion and the second channel region are characterized as channelregions for first conductivity type devices; wherein the firstconductivity type devices are characterized as PMOS devices.
 10. Themethod of claim 9, where forming the first gate dielectric device andthe second gate dielectric device further comprises depositing a gateelectrode material over the second high-k dielectric layer.
 11. Themethod of claim 9, further comprising epitaxially growing a compressivesilicon germanium layer on the first channel region of the semiconductorsubstrate prior to depositing the first high-k dielectric layer.
 12. Themethod of claim 11, where forming the first gate dielectric devicecomprises: depositing a first high-k dielectric layer ofHf_(x)Si_(1-x)O_(y) or Hf_(x)Si_(1-x)O_(y)N_(z) over the compressivesilicon germanium layer; and depositing a second high-k dielectric layerof HfO₂ over the first high-k dielectric layer.
 13. The method of claim12, where forming the second gate dielectric device comprises depositingthe second high-k dielectric layer of HfO₂ over the second channelregion.
 14. The method of claim 11, where forming the first gatedielectric device comprises depositing the first high-k dielectric layeras a silicate or metal oxy-nitride material in a deposition processwhich occurs at a temperature that is selected to reduce or eliminategermanium diffusion from the compressive silicon germanium layer. 15.The method of claim 9, further comprising epitaxially growing a siliconcarbide layer on the first channel region of the semiconductor substrateprior to depositing the first high-k dielectric layer.
 16. The method ofclaim 9, further comprising: forming a third gate dielectric device in athird region of the semiconductor substrate, wherein the third gatedielectric device comprises a third gate dielectric formed by depositingthe first high-k dielectric layer and the second high-k dielectric layerover a third channel region of the semiconductor substrate; and forminga fourth gate dielectric device in a fourth region of the semiconductorsubstrate, wherein the fourth gate dielectric device comprises a fourthgate dielectric that is thinner than the third gate dielectric and thatis formed by depositing the second high-k dielectric layer over a fourthchannel region of the semiconductor substrate; wherein the third channelregion and the fourth channel region are characterized as channelregions for second conductivity type devices, the second conductivitytype devices are of a conductivity type that is opposite to aconductivity type of the first conductivity type devices.
 17. A methodfor forming a semiconductor device comprising: providing a semiconductorsubstrate comprising first and second device areas, wherein the firstdevice area and the second device area are each characterized as a firstconductivity type device area; selectively forming a first depositedhigh-k dielectric layer over the first device area, where the firsthigh-k dielectric layer has a first dielectric constant value of 7.0 orgreater; forming a second deposited high-k dielectric layer over thefirst high-k dielectric layer in the first device area and over thesemiconductor substrate in the second device area, where the secondhigh-k dielectric layer has a dielectric constant value that is higherthan the first dielectric constant value; forming one or more gateelectrode layers over the second high-k dielectric layer; andselectively etching the one or more gate electrode layers to form one ormore gate electrode structures over the first and second device areas;wherein a first device formed in the first device area is characterizedas a PMOS transistor that includes a portion of the first depositedhigh-k dielectric layer and a portion of the second deposited high-kdielectric layer and a second device formed in the second device area ischaracterized as a PMOS transistor that includes a portion of the seconddeposited high-k dielectric layer and does not include a portion of thefirst deposited high-k dielectric layer; wherein the first device areaand the second device area are each characterized as a PMOS device area.18. The method of claim 17, further comprising epitaxially growing acompressive silicon germanium layer on one or more PMOS channel regionsof the semiconductor substrate in the first and second device areasprior to forming the first deposited high-k dielectric layer.
 19. Themethod of claim 18, where selectively forming the first deposited high-kdielectric layer comprises depositing a layer of Hf_(x)Si_(1-x)O_(y) orHf_(x)Si_(1-x)O_(y)N_(z) over at least the compressive silicon germaniumlayer in a deposition process which occurs at a temperature that isselected to reduce or eliminate germanium diffusion from the compressivesilicon germanium layer.
 20. The method of claim 17, where selectivelyforming the first deposited high-k dielectric layer comprises:depositing the first deposited high-k dielectric layer as a layer ofsilicate or metal oxy-nitride over the first and second device areas;and selectively etching the first deposited high-k dielectric layer fromthe second device area to expose the semiconductor substrate in thesecond device area.
 21. The method of claim 17, where forming the secondhigh-k dielectric layer comprises depositing a layer of HfO₂ over thefirst high-k dielectric layer in the first device area and over thesemiconductor substrate in the second device area.
 22. The method ofclaim 17, where selectively forming the first deposited high-kdielectric layer over the first device area reduces a thickness measurefor the first deposited high-k dielectric layer in the first device areathat is required to meet a predetermined electrical oxide thickness(Tox) requirement as compared to forming the first deposited high-kdielectric layer with a material having a higher dielectric constantvalue.
 23. A semiconductor fabrication process comprising: selectivelyforming a first high-k dielectric layer in a PMOS region of asemiconductor substrate, where the first high-k dielectric layer isformed from a first dielectric material which has a first high-kdielectric constant value; and forming a second high-k dielectric layerover the first high-k dielectric layer in the PMOS region and over anNMOS region of the semiconductor substrate, where the second high-kdielectric layer is formed from a second dielectric material which has ahigh-k dielectric constant value that is higher than the first high-kdielectric constant value.
 24. The semiconductor fabrication process ofclaim 23, further comprising depositing one or more gate electrodelayers over the second high-k dielectric layer.
 25. The semiconductorfabrication process of claim 24, further comprising selectively etchingthe one or more gate electrode layers to form one or more gate electrodestructures over the PMOS and NMOS regions.